The demand for Complementary Metal-Oxide-Semiconductor (CMOS), Charge Coupled Device (CCD), and other image input image sensors has increased as their characteristics have improved. Turning to FIG. 18, a circuit diagram for one picture element (pixel) PX of a CMOS image sensor is shown. Each pixel comprises a photodiode PD that receives light and generates and stores a photocharge, a transfer transistor T that transfers the photocharge from photodiode PD, a floating diffusion FD to which the photocharge is transferred by means of transfer transistor T, a reset transistor RS that is connected to the floating diffusion FD for discharging the photocharge in floating diffusion FD, an amplifying transistor (source follower) SF that converts the photocharge in floating diffusion FD into a voltage signal and amplifies it and whose gate electrode is connected to floating diffusion FD, and a selection transistor X for selecting pixels, thereby constituting a so-called 4-transistor CMOS pixel sensor. The 4 transistors can each be an N-channel MOS transistor.
In a CMOS image sensor, multiple pixels that are configured as described above are arranged in the form of an array; in each pixel, drive lines φT and φR are respectively connected to the gate electrodes of transfer transistor T and reset transistor RS, and a pixel selection line SL (φx), which is driven from a row transistor, is connected to the gate electrode of selection transistor X. A prescribed supply voltage VR is applied to the source/drain (output side) of either reset transistor RS or selection transistor X, current source CS is connected to the source/drain (output side) of amplifying transistor SF and an output line VOUT that is controlled by a column shift register so that a voltage signal is output.
FIG. 19 is a circuit diagram showing the overall circuit configuration of the CMOS image sensor. Multiple pixels are arranged in the form of an array on the photosensitive surface. The figure shows four pixels (PX1-PX4) as a representative example; the set of pixels in this configuration is repeated in the row and column directions. Connected to each pixel PX are supply voltage VR, ground GND, and drive lines (φT, φR, φx) that are controlled by a row shift register SRV. Each pixel is controlled by a column shift register SRH and drive lines (φNS, φN). As explained below, a charge signal (S)+CFD noise (N) and a CFD noise (N) signal are output from each pixel to each output line at their respective timing through an analog memory AM that that can be cleared by drive line φXCLR.
FIG. 20 is a circuit diagram analogous to the output portion of each pixel of the CMOS image sensor. The source/drain (output side) of the amplifying transistor SF comprising each pixel is connected to a constant current source (called current source hereafter) CS. When Vin is input from the floating diffusion to the gate of amplifying transistor SF, current ICS corresponding to the output voltage from output line VOUT flows to current source CS. The output line VOUT is connected to an analog memory capacitor CAM via a switch SW, so that when switch SW is closed, a charge corresponding to the output voltage is stored in analog memory capacitor CAM. Parasitic capacitance CLINE is also present in output line VOUT, giving total capacitance CTOTAL=CAM+CLINE. In the circuit shown in FIG. 20, output voltage VOUT is represented by equation (1) below as a function of current I.
                              V          OUT                =                              V            IN                    -                                    V              TH                        ⁡                          (                              V                OUT                            )                                -                                                                      2                  ⁢                  I                                                                      μ                    n                                    ⁢                                      C                    ox                                                              ·                              L                W                                                                        (        1        )            The lower limit of output voltage is determined at the point where the current source transistor barely operates in the saturation region, and the output voltage range decreases in proportion to the square root of the current. The power consumption increases with current.
FIG. 21 illustrates the equation (1) in the form of a graph showing the output voltage to output line VOUT versus the input voltage VIN. The broken line is a straight line, with VIN=VOUT. Output voltage VOUT falls by ΔV relative to input voltage VIN, and ΔV is proportional to √I, as shown by equation (1). At the same time, the value of output voltage VOUT varies from the output start time, and the time required until output voltage VOUT stabilizes is represented by equation (2) below.
                    t        =                                                            (                                                      V                    DARK                                    -                                      (                                                                  V                        IN                                            -                                              V                        TH                                                              )                                                  )                            ⁢                              C                TOTAL                                                    I              CS                                +                                    2              ⁢                              C                TOTAL                                                                                                                                2                      ⁢                      I                                                                                      μ                        n                                            ⁢                                              C                        ox                                                                              ·                                      W                    L                                                  ⁢                                  I                  CS                                                                                        (        2        )            Here, VDARK is the vertical signal line and analog memory reset voltage, and CTOTAL is CTOTAL=CAM+CLINE, as described above. To calculate speed, switch SW is closed, and the discharge speed of the charge stored in the two capacitors above is calculated. From Equation (2), the time required for output will be faster the larger the current ICS of bias current source CS.
FIG. 22 illustrates the equation (2) in the form of a graph showing the change in output voltage of output line VOUT versus time for three different magnitudes of current ICS lowing through current source CS (when current ICS is a small value (a), an intermediate value (b) and a large value (c)). Voltage at time 0 is voltage VDARK that corresponds to the output when there is no input voltage, that is, a dark signal; the larger the current ICS, the lower the voltage VDARK, and the smaller the current ICS, the higher the voltage VDARK. The output voltage of output line VOUT drops with time from voltage VDARK at time 0 and reaches a constant value at a certain voltage. As current ICS increases, VDARK and the output voltage of output line VOUT at the constant value decreases, and as current ICS decreases, VDARK and the voltage increase, like the magnitude of voltage VDARK at time 0. The time until a constant voltage value is reached from voltage VDARK at time 0 described above varies depending upon the magnitude of current ICS; thus, the time until a constant value is reached increases as the current ICS decreases. As is clear from equations (1) and (2), the source follower output voltage range or power consumption and speed are in a trade-off relationship, relative to the bias current source.
There is, therefore, a need for a circuit that addresses the concern the fact that the magnitude of the current of the current source varies during the sampling of the output voltage from the pixels, and that sampling may occur before the output value from the pixels has reached a constant value.